description the uc3870 family of synchronous step-down (buck) regulators provides high efficiency power conversion from an input voltage range of 4.5 to 36 volts. the uc3870 is tailored for battery powered applications such as lap - top computers, consumer products, communications systems, and aero - space which demand high performance and long battery life. the synchronous regulator replaces the catch diode in the standard buck regu - lator with a low rds(on) n-channel mosfet switch allowing for significant efficiency improvements. the high side n-channel mosfet switch is driven out of phase from the low side n-channel mosfet switch by an on-chip bootstrap circuit which requires only a single external capacitor to develop the regulated gate drive. fixed frequency, average current mode control provides the regulator with inherent slope compensation, tight regu - lation of the output voltage, and superior load and line transient response. switching frequencies up to 300khz are possible. the uc3870-1,-2 is designed to interface directly with precision references like the uc3910. when combined with the uc3910, output voltages be - tween 2v to 3.5v in 100mv increments and 1% accuracy are attainable. this makes the uc3870-1,-2 ideal for powering high performance micro- processors like the intel pentium ? pro and others. (continued) high efficiency, synchronous, step-down (buck) controllers features ? operation to 36v input voltage ? fixed frequency average current mode control ? 2v to 3.5v output voltage when combined with uc3910 precision reference/dac ? drives external n-channel mosfets for highest efficiency ? sleep mode current <75 a ? complementary 1 amp outputs with regulated gate drive voltage ? ldo (low drop out) virtual 100% duty cycle operation ? non-overlapping gate drives slus288a - august 1998 - revised october 2001 block diagram uc1870 -1/ -2 uc2870 -1/ -2 uc3870 -1/ -2 udg-96158 pin numbers refer to the dil-18 package.
2 uc1870 -1/ -2 uc2870 -1/ -2 uc3870 -1/ -2 dil-18 (top view) j or n, dw packages absolute maximum ratings supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36v boost voltage (boot). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50v output drivers (hdrive, ldrive) currents (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25a (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1a vref current. . . . . . . . . . . . . . . . . . . . . . . . . . internally limited inputs (vsns, ss, comp, ct) . . . . . . . . . . . . . . . . ?0.3 to 10v inputs (cmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 to 7.5v inputs (isns+, isns-) . . . . . . . . . . . . . . . . . . . . . . . ?0.3 to20v outputs (cao) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 to10v soft start sinking current . . . . . . . . . . . . . . . . . . . . . . . . 1.5ma storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . +300c all currents are positive into, negative out of the specified ter- minal. all voltages are referenced to gnd. consult packaging section of databook for thermal limitations and considerations of packages. connection diagrams a low power sleep mode can be invoked through the ss pin. quiescent supply current in sleep mode is typically less than 50 a. two uvlo options are available. the uc3870-1 is designed for logic level mosfets and has uvlo turn-on and turn-off thresholds of 4.5v and 4.4v respectively. the uc3870-2 is designed for standard power mosfets and has uvlo turn-on and turn-off thresholds of 10v and 9v respectively. a precision 2.5v reference can supply 20ma to external circuitry. an error amplifier with soft start, high bandwidth current amplifier, and a synchronizable oscillator are additional features. available packages include 18-pin plastic and ceramic dip (n, j), 18-pin soic (dw), and 20-pin plastic and ceramic leadless chip carriers (q, l). description (continued) plcc-20 (top view) j or n, dw packages plcc-20 (top view) j or n, dw packages
3 uc1870 -1/ -2 uc2870 -1/ -2 uc3870 -1/ -2 electrical characteristics: unless otherwise stated these specifications apply for t a = ?55c to +125c for uc1870x; ?25c to +85c for uc2870x; 0c to +70c for uc3870x; vcc = 12v, c t = 680pf, c cap = 1 f; c boot = 0.1 f, t a =t j . parameter test conditions min typ max units overall section supply current, sleep softstart=0v; t a = 25c 30 75 a supply current, operating 8.5 12 ma vcc turn-on threshold ucx870-2 10 10.5 v ucx870-1 4.5 4.8 v vcc turn-off threshold ucx870-2 8.2 9 v ucx870-1 4.1 4.4 v voltage amplifier section input voltage offset t a = 25c ?30 0 30 mv vsns bias current ?500 25 500 na transconductance i comp = + 10 a to ?10 a; uc3870 -1, -2; uc2870 -1, -2; 400 675 1000 mho i comp = + 5 a to ?5 a; uc1870 -1, -2 250 675 1250 mho v out high 2.8 3.1 3.25 v v out low 0.15 1 v output source current v out = 1v; uc3870 -1, -2; uc2870 -1, -2; 10 35 a v out = 1v; uc1870 -1, -2 5 35 a current amplifier section input offset voltage v comp = 2.5v ?6 0 6 mv input bias current(sense) v cm = 2.5v ?500 500 na open loop gain v cm = 2.5v, v out = 1v to 3.5v 80 110 db v out high r caout = 100k to gnd, t a = 25c 3.6 3.7 v v out low r caout = 100k to vref, t a = 25c 0.7 0.86 v output source current v out = 0v, t a = 25c 80 100 120 a common mode rej ratio v cm = 2v to 3v 70 90 db gain bandwidth product f in = 100khz, 10mv p-p 2 3.5 mhz reference section output voltage i ref = 0ma, t a = 25c 2.462 2.5 2.538 v i ref = 0ma 2.437 2.5 2.563 v load regulation i ref = 0ma to 5ma 2 15 mv line regulation vcc = 12v to 24v 2 15 mv short circuit current vref = 0v 10 20 25 ma uc 870 ? ordering information uvlo turn on/off threshold package temperature range 1: 4.5v/4.4v j: ceramic dil-18 1: ?55c to +125c 2: 10v/9v n: plastic dil-18 2: ?40c to +85c dw: soic-18 3: 0c to +70c
4 uc1870 -1/ -2 uc2870 -1/ -2 uc3870 -1/ -2 electrical characteristics: unless otherwise stated these specifications apply for t a = ?55c to +125c for uc1870x; ?25c to +85c for uc2870x; 0c to +70c for uc3870x; vcc = 12v, c t = 680pf, c cap = 1 f; c boot = 0.1 f, t a =t j . parameter test conditions min typ max units oscillator section initial accuracy t a = 25c 85 100 115 khz voltage stability vcc = 12v to 18v 1 1.5 % total variation line, temperature 80 120 khz ramp amplitude (p-p) t a = 25c 2.48 2.7 2.85 v ramp valley voltage t a = 25c 0.86 0.95 v sleep/soft start/bootstrap section sleep threshold measured on ss, t a = 25c 0.25 0.6 0.8 v ss charge current v ss = 2.5v 4 6 10 a ss discharge current v ss = 2.5v 0.5 0.8 ma bootstrap regulation voltage ucx870-2, low driver on 9.5 10.2 12.5 v ucx870-1, low driver on 6 7.5 9 v bootstrap refresh voltage ucx870-2, v caout >v ctpeak 789v ucx870-1, v caout >v ctpeak 2.7 3.5 4 v high side driver output section output high voltage i out = ?50ma, boot = 23v 21 22.2 v output low voltage i out = 50ma 1 2.2 v i out = 10ma 300 500 mv output low (uvlo) i out = 50ma, vcc = 0v 0.9 1.5 v output rise time c out = 1nf 40 160 ns output fall time c out = 1nf 30 100 ns low side driver output section output high voltage i out = ?50ma, v cap = 11v 8.8 9.5 v output low voltage i out = 50ma 1 2.2 v i out = 10ma 300 500 ma output low (uvlo) i out = 50ma, vcc = 0v 0.9 1.5 v output rise/fall time c load = 1nf 40 160 ns output fall time c out = 1nf 30 100 ns x10 amplifier section gain v isns v isns = 20mv to 80mv 9.2 10 10.4 v/v slew rate rising t a = 25c 1 1.4 v/ s slew rate falling t a = 25c 2 3.5 v/ s input resistance t a = 25c 60 100 165 k/
5 uc1870 -1/ -2 uc2870 -1/ -2 uc3870 -1/ -2 boot: this pin provides the high side rail for the hdrive output. an external capacitor (cbst) is connected between this pin and the drain of the external low side mosfet. when the low side mosfet is conducting cbst is charged to 11v (uc3870-2), 7.5v (uc3870-1), via an external diode tied to cap. when the low side mosfet turns off and the high side mosfet turns on, the cbst bootstraps itself up with the source of high side mosfet, ultimately providing a 10v vgs for the upper mosfet. since this 10v is referenced to the source of the high side n-channel mosfet, the actual voltage on boot and hdrive is approximately 10v above vcc while the high side mosfet is conducting. the voltage on boot is continuously monitored during low input voltage conditions when the duty cycle equals approximately 100% to insure that a sufficient gate drive level is being supplied by the uc3870. if the voltage on boot falls below 8v (uc3870-2) or 3.5v (uc3870-1), the ic forces the low side driver to cycle itself on for the few cycles required to replenish cbst. in this way, virtual 100% duty cycle operation is provided. ca-: this is the inverting input to the current amplifier. connect a series resistor and capacitor between this pin and cao to set the current loop compensation. an input resistor between this pin and isout provides the induc- tor current sense signal to the amplifier and also sets the high frequency gain of the amplifier. the common mode operating range for this input is between gnd and 4v. the normal range during operation is between 2v and 3v. cao: this is the output of the wide bandwidth current amplifier and one of the inputs to the pwm duty cycle comparator. the output signal generated by this amplifier commands the pwm to force the correct duty cycle to maintain output voltage in regulation. the output can swing from 0.1v to 4v. cap: a capacitor is normally connected between this pin and gnd providing bypass for the internal 11v (uc3870-2) and 7.5v (uc3870-1) regulator. charge is transferred from this capacitor to cbst via an external di - ode when the low side mosfet is conducting. if vcc 10v logic level mosfets are generally specified. cap should then be shorted to vcc in conjuncton with a low vf schottky to boot to maximize the gate drive ampli - tude. this technique provides adequate gate drive signal amplitudes with vcc as low as 4.5v. for high input volt - age applications, a simple external shunt zener regulator circuit can be connected to cap, thereby offloading power dissipation requirements from the ic to an external transistor. comp: this is the output of the voltage amplifier. it pro - vides the current command signal to the current ampli - fier. the voltage is clamped to approximately 3.2v. cmd: this is the non-inverting input of the voltage error amplifier. the voltage applied to cmd sets the output voltage of the power converter. the 2v to 3.5v input common mode range allows for direct interfacing to the uc3910 dac/precision reference. ct: a capacitor from ct to gnd sets the pwm oscillator frequency according to the following equation: f ct 1 14250 . use a high quality ceramic capacitor with low esl and esr for best results. a minimum ct value of 220pf in - sures good accuracy and less susceptibility to circuit lay - out parasitics. the oscillator and pwm are designed to provide practical operation to 300khz. gnd: all voltages are measured with respect to this pin. all bypass capacitors and timing components except those listed under the pgnd pin description should be connected to this pin. component leads should be as short and direct as possible. hdrive, ldrive: the outputs of the pwm are totem pole mosfet gate drivers on the hdrive and ldrive pins. the outputs can sink approximately 1a and source 500ma. this characteristic optimizes the switching tran- sitions by providing a controlled dv/dt at turn-on and a lower impedance at turn-off. these are complementary outputs with a typical deadtime of 200ns. internal cir - cuitry prevents the possibility of simultaneous conduction of the output mosfets (shoot through). hdrive is the high side bootstrapped output. its upper power supply rail is the boot pin which means that its output will fly approximately 10v above vcc when the upper side of the totem pole output is conducting. the power supply rail for ldrive is cap. as a result the vgs of both gates are regulated to approximately 10v if vcc is >11v. a series resistor between these pins and the mosfet gates of at least 10 ohms can be used to control ringing. additionally, a low vf schottky diode should be con - nected between these pins and gnd to prevent sub - strate conduction and possible erratic operation. isns?: this is the inverting input to the x10 instrumen - tation amplifier. the common mode input range for this pin extends from gnd to vcc. a low value resistor in series with the output inductor is connected between this pin and isns+ to develop the current sense signal. pin descriptions
6 uc1870 -1/ -2 uc2870 -1/ -2 uc3870 -1/ -2 isns+: this is the non-inverting input to the x10 instru - mentation amplifier. the common mode input range for this pin extends from gnd to vcc. isout: this is the output of the x10 instrumentation am - plifier. the output voltage on this pin is level shifted 2v above gnd, such that if a 100mv differential input is ap - plied across isns+ and isns?, the output will be 3v. pgnd: this is the high current ground for the ic. the mosfet driver transistors are referenced to this ground. for best performance an external star ground connection should be made between this pin, the source of the low side mosfet, the capacitor on cap, the anodes of any external schottky clamp diodes and the output filter ca - pacitor. as with all high frequency layouts, a ground plane and short leads are highly recommended. ss: a capacitor from this pin to gnd in conjunction with an internal 10 a current source provides a soft start function for the ic. the voltage level on ss clamps the output of the voltage amplifier through an internal buffer, thus providing a controlled startup. the ss time is ap- proximately: c v v v a ss o in 3 10 once the device has completed its soft start cycle, a low power sleep mode can be invoked by pulling ss below 0.5v typically. in sleep mode, all of the device functions are disabled except for those which are required to bring the device out of sleep mode when ss is released. typi - cal sleep mode supply current is less than 50ma. vcc: positive supply rail for the ic. bypass this pin to gnd with a 1mf low esl/esr ceramic capacitor. the maximum voltage for vcc is 36v. the turn on voltage level on vcc is 4.5v with 100mv of hysteresis for the uc3870-1 and 10v with 1v of hysteresis for the uc3870-2. vref: v ref is the output of the precision reference. the output is capable of supplying 20ma to peripheral circuitry and is internally short circuit current limited. vref is disabled and low whenever vcc is below the uvlo threshold, and when ss is pulled below 0.5v. a vref ?good? comparator senses vref and disables the pwm stage until vref has attained approximately 90% of its nominal value. bypass vref to gnd with a 0.1mf ceramic capacitor for best performance. vsns: this pin is the inverting input of the voltage am- plifier and serves as the output voltage feedback point for the synchronous regulator. it senses the output volt- age through a voltage divider which produces a nominal 2v. pin descriptions (continued) the uc3870 employs a fixed frequency average current mode control buck topology to convert a higher battery voltage down to a tightly regulated output voltage. spe - cial design techniques allow this bipolar ic to deliver ex - ceptional performance while consuming approximately 6ma of supply current over an input voltage range of 4.5 to 35 volts. fixed frequency operation allows synchroni - zation to an existing system clock, and easier filtering. average current mode control provides inherent slope compensation and accurate short circuit current limiting. the output inductor current is sensed by an external low value shunt resistor (r sense ). this signal at full load current should be no larger than 100mv in order to mini - mize sensing losses. the differential voltage across rsense is amplified by the internal x10 instrumentation amplifier. the common mode input range for this ampli - fier extends from gnd to vcc in order to maintain accu - rate current sensing under normal conditions as well as abnormal conditions such as output short circuit and low drop out (ldo) modes. the output of the x10 instrumentation amplifier is applied to the inverting input of the current amplifier through an external resistor. the converter?s output voltage feedback is applied to the vsns pin through an external voltage divider. the differ - ence between the voltage at vsns and the voltage at the non-inverting input is amplified by the voltage ampli - fier and applied to the non-inverting input of the current amplifier. this instantaneous reference level forms the current command input for the average current control loop. the average current amplifier develops the duty cy - cle command signal by integrating the current feedback signal with respect to the instantaneous current com - mand input. this output is compared to the fixed high amplitude oscillator ramp waveform at the inputs of the pwm comparator to develop duty cycle information for the pwm drive. the large amplitude oscillator ramp pro - vides both high noise margin and built-in slope compen - sation in average current mode control methodology. the fixed frequency oscillator is programmed with a sin - applications information
7 uc1870 -1/ -2 uc2870 -1/ -2 uc3870 -1/ -2 gle external capacitor connected between ct and gnd, and is capable of switching frequencies up to 300khz. the uc3870 can be synchronized to an external clock by capacitively coupling the signal to the junction of the capacitor at ct and a low value resistor tied to gnd. re - fer to application note u-111. the pwm drive signal is applied to the complementary output driver stages. since the high side switch is an n?channel mosfet, a means for driving its gate above vcc is required. this is accomplished via the internal 11v (uc3870-2)/7.5v (uc3870-1) regulator and an ex - ternal capacitor (c bst ). c bst is charged through an ex - ternal diode to vcc or cap when the low side mosfet is on. the charging level on c bst is internally regulated to 11v or 7.5v minus an external diode drop by the uc3870 as long as vcc is above 11v. when the low side mosfet turns off, c bst is applied across the gate to the source of the upper mosfet allowing it to begin turn-on. as the upper mosfet turns on, it lifts or boot - straps the low end of c bst , along with its source. shortly thereafter, the source voltage level is reduced by rds(on) i load below vcc. when vcc < 10v, v gs for the high side mosfet is approximately equal to vcc. if vcc < 8v, logic level mosfets are recommended. in these applications, cap should be shorted to vcc and an external schottky diode is connected between cap/vcc and boot. for low battery applications, a syn - chronous regulator must be capable of ldo or 100% duty cycle operation. the uc3870 includes circuitry to insure that this mode of operation is possible even though it uses a bootstrapped drive technique for the high side mosfet. during commanded 100% duty cycle operation, the uc3870 monitors the v gs drive signal ap - plied to the high side mosfet, and automatically pro - vides complementary pulses to refresh the bootstrap capacitor when this voltage falls below a set threshold. in this way, near 100% duty cycle operation is possible, with effective duty cycle dependent only upon the value of c bst . high efficiency is obtained primarily by the low side mosfet which replaces the schottky diode in the stan - dard buck configuration. its low r ds(on) produces a much lower voltage drop than a low vf schottky diode. as output voltages get lower, these improvements be - come more evident. another efficiency consideration is the the possibility of reverse current in the output inductor. for a non- synchronous regulator this isn?t a problem since the di - ode will block reverse current, allowing discontinuous in - ductor current operation at light loads. since the synchronous regulator replaces the diode with a switch, reverse current can and will flow if the low side switch is on when the inductor is depleted. the uc3870 includes circuitry to prevent reverse current from flowing in the in - figure 1. typical application: uc3870-1, -2 pentium pro power converter application information (continued) udg-96159
8 uc1870 -1/ -2 uc2870 -1/ -2 uc3870 -1/ -2 4 5 6 7 8 9 10 11 -75 -25 25 75 125 temperature c i cc (ma) typical performance information figure 1. supply current ductor by disabling the low side gate drive signal during discontinuous mode operation. this increases efficiency by eliminating unnecessary i 2 r losses in the mosfet and the inductor. soft start is recommended for buck converters to reduce stress on the power components during startup, and to reduce overshoot of the output voltage. this improves reliability. the uc3870 includes a user programmable soft start pin to implement this feature. an internal 10ma current source charges the external soft start capacitor which provides a clamp at the output of the voltage amplifier. an ultra low power sleep mode is also invoked from the ss pin. a voltage level below 0.5v on this pin reduces total standby current to less than 50ma. short circuit protection is inherent to the average current mode technique with proper compensation of the current amplifier. to prevent operation of the mosfets with an inadequete drive signal, an undervoltage lockout circuit suppresses the output drivers until the input supply voltage is sufficiently high enough for proper operation. the uc3870-1 is intended for applications with logic level mosfets and its vcc turn-on and turn-off thresholds are 4.5v/4.4v respectively. the uc3870-2 is intended for applications with standard mosfets and has uvlo turn-on and turn-off thresholds of 10v and 9v respectively. the precision 2.5v reference can provide 10ma to power external circuitry. the reference output is disabled during uvlo and sleep modes. application infomation (continued) 560 600 640 680 720 760 -50 -25 0 25 50 75 100 temperature c transconductance (umho) figure 2. volt amp gm (i out =10 a) 80 90 100 110 120 130 140 -75 -25 25 75 125 temperature c frequency (khz) figure 3. oscillator frequency vs. temperature (ct = 680pf)
9 uc1870 -1/ -2 uc2870 -1/ -2 uc3870 -1/ -2 75 80 85 90 95 100 105 -75 -25 25 75 125 temperature c % duty cycle figure 5. high drive maximum duty cycle (uc1870-1,-2) 0.08 0.1 0.12 0.14 0.16 012345 vcm (v) vsc (v) 0 70 room figure 4. short circuit limit voltage reflected to input of current amp vs. current amp common mode voltage typical performance info (continued) 0 0.04 0.08 0.12 0.16 0.2 024681012 vcm (v) vos (v) +3 std mean ?3 std figure 6. i limit voltage tolerance vs. vcm
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